Hardware Acceleration for AI at the Edge

Focus on hardware-aware algorithmic techniques for high-performance machine learning and edge AI accelerators, such as FPGA. Research topics: 1). Sparse and fast linear transform DNNs. A distinct ingredient in my research work is the strong presence of analytical components and their translation into a practical realization of compact hardware-friendly DNNs by the blooming era of edge AI. A revamped design of the linear transform and a regularized hardware architecture. This task targets a field-programmable gate array (FPGA) realization of dedicated NN chains. Vivado high-level synthesis (HLS) tools to compile algorithmic descriptions (e.g., C/C++, Python) to RTL designs for quick ASIC or FPGA implementation of hardware accelerators. Furthermore, an ASIC can be designed to achieve this research goal. 2). Heterogeneous distributed platform: research on an FPGA/ASIC-accelerated heterogeneous architecture provides resource management and programming support for computing-intensive applications. We need to further find a way to the interdependence among these different customization techniques on several hardware architectures(CPU/GPU/ASIC/FPGA), allowing designers to balance various performance/area/accuracy trade-offs.

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